(a) Field of the Invention
The present invention relates generally to semiconductor manufacturing processes and, more particularly, to techniques for passivating semiconductor devices.
(b) Description of Related Art
Semiconductor devices, such as gallium arsenide field effect transistors (GaAs FETs) are commonly used in, for example, military and commercial microwave communications circuitry. The pseudomorphic high electron mobility transistor (PHEMT) is one type of GaAs FET that is regularly used in, for example, solid state power amplifiers within satellite and other space-based communication systems, such as L-band and C-band commercial satellite systems and X-band, Ku-band, and V-band military satellite systems. Because semiconductor devices, such as pHEMTs, are located within satellites and other sophisticated communications equipment, it is necessary that these devices last a considerable amount of time and are immune to the deteriorating effects of elements within the environment in which they are used. Without such immunity, oxygen, hydrogen, water, etc., will operate to modify the electrical characteristics of these devices over time. For example, semiconductor devices exposed to hydrogen (which is emitted even by components located within satellite packages in space) generally demonstrate a shift or a gradual drift in the pinch-off voltage and in the optimum gate voltage thereof, which reduces the maximum transconductance and the maximum output power of these devices.
It is common practice to encapsulate semiconductor devices, such as a pHEMTs, in an inert material to isolate the device from its immediate environment and, thereby, to protect the device from oxygen, water, etc. within the environment. In general, all Group III-V FETs employ some form of encapsulation process to protect these devices from airborne or space-borne contaminants, particulates, and humidity. This encapsulation process also passivates these semiconductor devices by terminating dangling bonds created during manufacture of the semiconductor devices and by adjusting the surface potential to either reduce or increase the surface leakage current associated with these devices.
Silicon nitride is commonly used to produce a passivation layer on semiconductor devices, such as GaAs metal semiconductor FETs (MESFETs), to prevent oxidation of the surfaces of these devices. In fact, silicon nitride is one of the most widely used materials for passivation layers on GaAs semiconductor devices due to the fact that this material is extremely chemically stable and has excellent barrier properties.
The most common technique used to deposit silicon nitride on GaAs semiconductor devices, such as discrete MESFET devices or MESFET devices incorporated as part of monolithic microwave integrated circuits, is the plasma enhanced chemical vapor deposition (PECVD) technique. In this context, the PECVD technique provides a plasma of reactant gases including silicon and nitrogen to a chamber in which a semiconductor is disposed. The gases are then reacted within the chamber to deposit a layer or film of silicon nitride on the surface of the semiconductor. While the gases may be reacted within the chamber at a temperature in the range of approximately 150xc2x0 C. to 350xc2x0 C., most PECVD techniques react the gases at temperature ranges between 200xc2x0 C. and 350xc2x0 C. to deposit silicon nitride on Group III-V semiconductors.
U.S. Pat. No. 5,223,458 discloses that silicon nitride, silicon monoxide, silicon dioxide, silicon oxynitride, or polymide can be used to produce a passivation layer on the surface of a GaAs semiconductor -device to isolate exposed surfaces of the GaAs device from an external environment. Likewise, U.S. Pat. No. 4,426,656 discloses a PECVD process that deposits a silicon nitride passivation layer on GaAs MESFETs to prevent oxidation of the exposed semiconductor surfaces of the devices. This process uses an ammonia to silane gas ratio in the range of 1.62 to 2.05 to produce a silicon nitride film or passivation layer that is under tensile stress and has a nominal index of refraction of 2.0.
However, it is generally recognized that silicon nitride passivation layers have undesirable characteristics and, in particular, that silicon nitride passivation layers tend to change the threshold and/or reverse breakdown voltages of the semiconductor devices on which they are used. In fact, a particular problem with the use of silicon nitride as a passivation layer in most semiconductor devices arises because silicon nitride layers tend to produce an undesirable reduction in the reverse breakdown voltage between, for example, the gate and drain electrodes of FET devices as well as between the drain and source electrodes of FET devices. This reduction in the reverse breakdown voltage reduces the effectiveness of such devices when used in, for example, power amplifiers.
Although silicon nitride passivation techniques have been improved in an attempt to minimize the reduction in the reverse breakdown voltage of the semiconductor devices on which they are used, these improved processes still cause some appreciable reduction in the reverse breakdown voltage. For example, U.S. Pat. No. 5,223,458, discloses a technique for passivating Group III-V MESFETs that reduces the degradation of the gate-to-drain breakdown voltage of these devices over other known passivation processes. The passivation process disclosed in this patent uses a plasma surface treatment to introduce an electro-negative species, such as 02, into the surface of the MESFET before applying a silicon nitride passivation layer onto the MESFET. However, in the disclosed example, this passivation process still reduced the average reverse breakdown voltage of the device from approximately 19.5 volts to approximately 18.0 volts.
Although it is known to use silicon nitride passivation layers in semiconductor devices, it is believed that prior art passivation processes only use passivation layers having a low silicon content similar to that of stoichiometric silicon nitride Si3N4, i.e., silicon-poor layers. It is also believed that all prior art silicon nitride passivation layers are under tensile stress. These facts may, in part, result from the generally accepted belief that using a high silicon content in a passivation layer, i.e., using a silicon-rich passivation layer, decreases the ability to dry-etch the device in subsequent processing.
The present invention relates to a silicon-rich, compressively stressed semiconductor passivation layer and to a passivation process that deposits a silicon-rich, compressively stressed passivation layer or thin film on a semiconductor device, such as a GaAs based power HEMT. This silicon-rich passivation layer produces a desirable encapsulant that provides for long life of the semiconductor device without significantly negatively effecting certain characteristics of the semiconductor device, such as the reverse breakdown voltage. In fact, this silicon-rich, compressively stressed passivation layer may increase the reverse breakdown voltage of the semiconductor device on which it is used which, in turn, enhances the effectiveness of the device in certain communication applications, such as in amplifiers. Furthermore, this silicon-rich, compressively stressed passivation layer does not reduce the ability to dry-etch the semiconductor device in subsequent processing.
The passivation technique of the present invention may use a PECVD process to produce a silicon-rich nitride film as a passivation layer on a semiconductor device. The silicon-rich film of the present invention has a relatively high index of refraction when compared to stoichiometric silicon nitride (Si3N4), for example, approximately 2.4, is compressively stressed, and has a very low hydrogen and oxygen content. Although this passivation layer may be applied to any semiconductor device, it is particularly useful when applied to Group III-V semiconductor devices such as GaAs semiconductor devices and Gallium Nitride (GaN) semiconductor devices.
According to one aspect of the present invention, a semiconductor device, such as a Group III-V semiconductor device, includes a compressively stressed nitride passivation layer disposed on a surface of a semiconductor material. The passivation layer may be compressively stressed to about 8xc3x97109 dynes/cm2 and, preferably, is compressively stressed to less than 1xc3x971010 dynes/cm2. Furthermore, the passivation layer may be low in hydrogen and oxygen content with respect to stoichiometric silicon nitride (Si3N4) and, preferably, has a hydrogen content below about twenty atomic percent and an oxygen content below about five atomic percent.
According to another aspect of the present invention, a semiconductor device, such as a Group III-V semiconductor device, includes a silicon nitride passivation layer disposed on a surface of a semiconductor material, wherein the silicon nitride layer is silicon-rich with respect to stoichiometric silicon nitride (Si3N4). The silicon-rich passivation layer may have a nitrogen/silicon ratio between about 0.5 and 0.9 and, preferably, has a nitrogen/silicon ratio of about 0.7.
According to still another aspect of the present invention, a semiconductor device, such as a Group III-V semiconductor device, includes a silicon nitride passivation layer having an index of refraction greater than or equal to about 2.2 disposed on a surface of a semiconductor material.
In accordance with yet another aspect of the present invention, a method of passivating a Group III-V semiconductor device includes the steps of placing the semiconductor device in a chemical deposition chamber, introducing silicon and nitrogen based gasses based into the chamber and reacting the gasses within the chamber to deposit a silicon nitride passivation layer on a surface of the semiconductor device that is silicon-rich with respect to stoichiometric silicon nitride (Si3N4). In addition or in the alternative, the gasses may be reacted to produce a passivation layer having an index of refraction greater than or equal to 2.2 and/or a passivation layer that is compressively stressed. Silane and ammonia may be introduced into the chamber as the silicon and nitrogen based gasses, respectively, at an ammonia to silane ratio of about 0.2.